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Samsung heir discusses world’s first 3-nm process for foundry

Samsung Electronics’ de facto leader Lee Jae-yong on Thursday discussed the tech giant’s strategy to utilize the world’s first 3-nanometer process technology for manufacturing chips.

Lee visited the company’s semiconductor research and development center in Hwaseong, Gyeonggi Province, as his first official gesture of on-site management in 2020.

The Samsung heir discussed the company’s plans to commercialize cutting-edge chips ordered from global customers on the latest 3-nm gate-all-around process technology under development, according to the firm. 


Samsung heir Lee Jae-yong shakes hands with engineers at the company’s semiconductor R&D center in Hwaseong, Gyeonggi Province, Thursday. (Samsung Electronics)
Samsung heir Lee Jae-yong shakes hands with engineers at the company’s semiconductor R&D center in Hwaseong, Gyeonggi Province, Thursday. (Samsung Electronics)


GAA is known as an architectural successor to the current FinFET technology, which enables chipmakers to push further the nanometer range for microchips.

Samsung completed the development of a 5-nm FinFET process tech based on extreme ultraviolet technologies in April last year. And it is working on the next-generation nanometer process tech.

Compared with the 5-nm process, the 3-nm GAA tech provides an increase of more than 35 percent in logic area efficiency with 50 percent lower power consumption and about 30 percent higher performance, the company said.

“Lee’s visit to the semiconductor R&D center once again highlights Samsung’s pledge to grow as a top chipmaker in the non-memory field,” said a Samsung spokesman.

Last year, Samsung announced a 133 trillion won ($111.85 billion) investment plan with the goal of becoming the world’s top maker of systems on chips by 2030.

By Song Su-hyun (song@heraldcorp.com)
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